NEET Semiconductor Electronics: Materials, Devices and Simple Circuits Previous Year Questions with Solutions

Compare the magnitude of the applied reverse bias voltage |V_i| with the Zener breakdown rating V_Z:

• • Because the input reverse voltage exceeds breakdown, avalanche/Zener breakdown occurs.
• • The ideal Zener diode clamps the potential difference between terminals C and B to exactly V_Z = 3 V.

The complete circuit loop consists of the DC voltage source, the Zener diode, and series resistor R:

• • V_R is the voltage difference across resistor R, which is connected between terminals B and A.
• • V_R = |V_B - V_A|.

Isolate the resistor voltage:

• • Matches Option (2) exactly.

Examine the connections of top branch containing diode D_1:

• • Positive terminal of 5 V battery is connected to p-type anode; negative terminal to n-type cathode.
• • External electric field opposes the built-in barrier field, narrowing the depletion region.

Examine the middle branch containing diode D_2:

• • Careful inspection of the circuit crop reveals an open gap in the lead after D_2.
• • Since the branch is open-circuited, zero current flows and zero voltage drops across the junction.
• • Depletion width W_2 equals the natural thermal equilibrium width W_0.

Examine the bottom branch containing diode D_3:

• • Diode D_3 is connected with p-type anode to negative rail and n-type cathode to positive rail.
• • Applied reverse bias aids the built-in barrier field, widening the space charge layer.

Combine all three regimes:

• • Matches Option (3) exactly.

The logic circuit consists of an upper NOR gate, a lower NAND gate, both receiving identical binary inputs A and B, feeding into an AND gate.

• • Y = (\overline{A + B}) \cdot (\overline{A \cdot B})

Apply De Morgan’s first and second laws to express the terms in product-of-sums / sum-of-products format:

• • Using the involution rule, A' · B' is universally equivalent to (A + B)', which is the definition of a NOR gate.

Verify all four input combinations (A, B):

• • The truth table [1, 0, 0, 0] is uniquely identical to a NOR gate.

Substitute t = 15 × 10⁻³ s into the input voltage waveform:

• • The input voltage is at its negative peak (-220 V).

In a center-tapped transformer, the secondary voltage is split equally into two halves with respect to the center tap (which serves as the zero-potential reference):

• • If the upper secondary terminal is negative relative to the center tap, diode D₁ (connected to the upper terminal) has its anode at negative potential ⟹ D₁ is reverse biased.
• • Concurrently, the lower terminal is positive relative to the center tap, so diode D₂ has its anode at positive potential ⟹ D₂ is forward biased.
• • This corresponds to Option (2).

The schematic does not specify dot convention on the transformer core:

• • Depending on the winding direction of the secondary coil, a negative input can produce a positive upper terminal, rendering D₁ forward biased and D₂ reverse biased (Option 1).
• • Recognizing this technical ambiguity, the National Testing Agency (NTA) officially declared the answer key as "A,B" (both Option 1 and Option 2 correct).

A solar cell is a p-n junction diode operated without any external bias voltage. When sunlight illuminates the depletion region, electron-hole pairs are photogenerated. The internal junction electric field sweeps electrons to the n-side and holes to the p-side, setting up a photo-voltage. When connected across a load, it supplies current. Because it supplies power rather than drawing power, the current flows out of the positive terminal, resulting in a negative current convention for positive voltage. Hence, the I-V curve lies in the IV quadrant.

When a p-n junction is reverse biased (p-side connected to negative terminal, n-side to positive terminal), the potential barrier height increases, completely blocking majority carriers from diffusing across the junction. The only current that flows is the reverse saturation current (order of microamperes, μA), which is caused solely by the drift of thermally generated MINORITY carriers (electrons from p-side and holes from n-side) swept across the depletion layer by the junction field. Therefore, the reverse current is due to minority carriers, not majority carriers.

Statement A is completely correct. Statement B falsely claims the reverse current is due to majority carriers. Therefore, "A is correct but B is incorrect", matching Option (3).

The top gate is a two-input NAND gate whose inputs are shorted together to receive a common signal A. The Boolean operation of a NAND gate on identical inputs simplifies directly to an inverter (NOT gate):

The bottom gate is a two-input NOR gate whose inputs are shorted together to receive a common signal B. The Boolean operation on identical inputs also simplifies to an inverter (NOT gate):

The signals Y_A = Ā and Y_B = B̄ serve as inputs to the final NOR gate. The output Y is the NOR operation on Ā and B̄:

Applying De Morgan’s law to the complement of a sum yields the product of the complements:

Examine the given truth table row by row: - Row 1: A = 0, B = 0 -> Y = 1 - Row 2: A = 0, B = 1 -> Y = 0 - Row 3: A = 1, B = 0 -> Y = 1 - Row 4: A = 1, B = 1 -> Y = 0

Writing the canonical minterms for the rows where the output Y is 1 (Row 1 and Row 3):

Factor out the common term B̄ using the distributive law:

For a bridge to achieve balance, the potential difference across the galvanometer G must be zero (V_top = V_bottom), which requires continuous current flow through all four resistive branches establishing a stable potential divider.

The DC source E is connected with its positive terminal on the left and negative terminal on the right. Current enters at the left node, divides into the upper and lower arms, and exits at the right node. In the bottom-right arm, the conventional current MUST flow from the lower central junction towards the right-hand junction connected to the negative terminal of the battery.

A p-n junction diode conducts current only when it is forward biased (p-side/anode at higher potential than n-side/cathode). In Circuit (3), the anode is connected to the bottom junction and cathode to the right junction, so it is forward biased and conducts freely. In Circuit (4), the diode is reverse biased, presenting near-infinite resistance and preventing current flow.

Therefore, only Circuit (3) allows proper forward-biased conduction through the diode in series with the 5 Ω resistor, making it the only circuit that can establish the required currents and achieve bridge balance.

A photovoltaic device (solar cell) operates on the principle of the photovoltaic effect. When incident photons of energy hν > E_g strike the junction, electron-hole pairs are generated in the depletion region. The built-in junction electric field separates electrons to the n-side and holes to the p-side, establishing a photo-voltage across an external load without any external bias:

A Zener diode is a special-purpose semiconductor diode that is heavily doped on both p and n sides, resulting in a very thin depletion layer (~10⁻⁶ m) and intense junction electric field (~5 × 10⁶ V/m). It is specifically designed to operate under reverse bias in the Zener breakdown region, where the voltage across it remains virtually constant despite sharp variations in current, serving as a voltage stabilizer:

Since both Statement I and Statement II represent foundational, canonical principles of semiconductor devices, Option (2) is the uniquely correct choice.

The output of a full-wave rectifier consisting of two p-n junction diodes and a center-tapped transformer is unidirectional but pulsates periodically with twice the input frequency (ripple frequency = 2f). This output consists of a desired DC component superimposed with unwanted AC ripple harmonics.

To obtain a steady DC voltage without fluctuations, a filter circuit is employed. A capacitor filter is connected in parallel with the load resistance R_L. Its capacitive reactance is frequency-dependent:

For the high-frequency AC ripple components, X_C is very low, providing an easy low-impedance bypass path. For DC (f = 0), X_C → ∞, meaning zero DC current leaks through the capacitor, forcing steady DC voltage across the load resistance R_L:

The given digital logic circuit contains two NOT gates (inverters) connected to inputs A and B, respectively. The outputs of these two inverters, Ā and B̄, serve as the inputs to a two-input NAND gate.

A NAND gate performs an AND operation followed by a negation. Therefore, the output Y is expressed as:

By De Morgan’s second theorem of Boolean algebra, the complement of a product of variables equals the sum of their individual complements:

The expression Y = A + B corresponds identically to a standard OR gate:

The drift velocity of a charge carrier under an electric field $E$ is $v_d = \mu E$, where $\mu$ is mobility. Current through a semiconductor of cross-sectional area $A$ with carrier concentration $n$ is:

For n-type with electron density $n_e$ and p-type with hole density $n_h$:

Electrons in n-type occupy the conduction band, where they behave almost as free electrons with small effective mass. Holes in p-type move via the sequential vacancy-hopping of bound valence electrons. Consequently, in all semiconductors (Silicon, Germanium, GaAs):

A Zener diode is a heavily doped silicon p-n junction diode. When operated in the reverse breakdown region, the voltage across the diode ($V_Z$) remains virtually constant over a wide range of reverse currents ($I_Z$). Therefore, to regulate unregulated DC voltage, it is always connected in reverse bias across the load:

In an unbiased p-n junction, diffusion of majority carriers creates a depletion layer with a built-in potential barrier $V_0$. For Germanium, $V_0 \approx 0.3\text{ V}$, and for Silicon (the ubiquitous material in modern electronics), $V_0 \approx 0.7\text{ V}$. Thus, the barrier potential typically lies between $0.3\text{ V}$ and $0.7\text{ V}$, not between $0.1\text{ V}$ and $0.3\text{ V}$. Statement (B) is unambiguously incorrect.

Statement (A) is correct and Statement (B) is incorrect. This corresponds uniquely to Option (3).

Analyze the logic gate circuit: - Gate 1 is an AND gate with inputs $A$ and $B$, giving output $Y_1 = A \cdot B$. - Gate 2 is a NAND gate with inputs $B$ and $C$, giving output $Y_2 = \overline{B \cdot C}$. - Gate 3 is an OR gate combining $Y_1$ and $Y_2$:

Construct the interval-by-interval digital truth table from the provided waveforms ($5\text{ V} \equiv 1$, $0\text{ V} \equiv 0$): - $0 < t < t_1$: $A = 0, B = 0, C = 1 \implies Y_1 = 0, Y_2 = \overline{0} = 1 \implies y = 0 + 1 = 1$ ($5\text{ V}$) - $t_1 < t < t_2$: $A = 1, B = 0, C = 1 \implies Y_1 = 0, Y_2 = \overline{0} = 1 \implies y = 0 + 1 = 1$ ($5\text{ V}$) - $t_2 < t < t_3$: $A = 0, B = 1, C = 0 \implies Y_1 = 0, Y_2 = \overline{0} = 1 \implies y = 0 + 1 = 1$ ($5\text{ V}$) - $t_3 < t < t_4$: $A = 1, B = 1, C = 0 \implies Y_1 = 1, Y_2 = \overline{0} = 1 \implies y = 1 + 1 = 1$ ($5\text{ V}$) - $t_4 < t < t_5$: $A = 0, B = 0, C = 1 \implies Y_1 = 0, Y_2 = \overline{0} = 1 \implies y = 0 + 1 = 1$ ($5\text{ V}$) - $t_5 < t < t_6$: $A = 1, B = 0, C = 1 \implies Y_1 = 0, Y_2 = \overline{0} = 1 \implies y = 0 + 1 = 1$ ($5\text{ V}$) - $t > t_6$: $A = 0, B = 0, C = 1 \implies Y_1 = 0, Y_2 = \overline{0} = 1 \implies y = 0 + 1 = 1$ ($5\text{ V}$)

The output $y$ is logic high ($5\text{ V}$) uniformly throughout all time intervals, corresponding to the straight horizontal line at $5\text{ V}$ in Graph (3).

During the formation of a p-n junction, holes diffuse from the p-side to the n-side and electrons from the n-side to the p-side. This uncovers immobile positively charged donor ions on the n-side and immobile negatively charged acceptor ions on the p-side, establishing a space-charge depletion layer devoid of free charge carriers and setting up an internal barrier electric field directed from n to p.

In reverse bias, the p-type region is connected to the negative terminal of the external battery and the n-type region to the positive terminal. The applied reverse voltage produces an external electric field in the SAME direction as the internal barrier field. Consequently, holes in the p-side are pulled away toward the negative terminal, and electrons in the n-side are attracted toward the positive terminal.

Because majority carriers are pulled away from the junction interface, an additional layer of ionized dopant impurity atoms is exposed on both sides of the junction. Therefore, the width of the depletion region increases, and the effective barrier height increases from $$V_0$$ to $$(V_0 + V)$$.

Under forward bias, the external field opposes the barrier field, pushing majority carriers into the depletion region and dramatically reducing its width.

A junction transistor has three distinct doped regions: 1. Emitter: Supplies majority charge carriers; it is moderately sized and HEAVILY DOPED. 2. Base: The central connecting region; it is EXTREMELY THIN (~few micrometers) and VERY LIGHTLY DOPED. 3. Collector: Collects carriers passing through base; it is physically the LARGEST in size (to dissipate heat) and MODERATELY DOPED.

- Statement (1) claims all regions have same doping: False, doping order is Emitter > Collector > Base. - Statement (2) claims all regions have same size: False, size order is Collector > Emitter > Base.

For normal transistor action (active amplification mode): - The emitter-base junction must be FORWARD BIASED. - The collector-base junction must be REVERSE BIASED. Statement (3) falsely claims both junctions are forward biased (which is the saturation regime, not normal active transistor action).

If the base were thick or heavily doped, most majority carriers injected from the emitter would recombine in the base and never reach the collector. The thin and lightly doped base ensures that only ~2-5% of carriers recombine ($$I_B$$ is very small), allowing >95% to cross into the collector ($$I_C \approx I_E$$). Hence, Statement (4) is the defining, correct statement.

- Input $$A$$ passes through a NOT gate, producing $$\bar{A}$$. - Input $$B$$ passes through a NOT gate, producing $$\bar{B}$$. - Signals $$\bar{A}$$ and $$\bar{B}$$ enter a two-input NOR gate.

The output of a NOR gate is the inverted sum of its inputs: $$Y = \overline{\bar{A} + \bar{B}}$$.

According to De Morgan's Theorem: $$\overline{X + Y} = \bar{X} \cdot \bar{Y}$$. Letting $$X = \bar{A}$$ and $$Y = \bar{B}$$: $$Y = \overline{(\bar{A})} \cdot \overline{(\bar{B})}$$ Since the double inversion of a Boolean variable returns the variable itself ($$\overline{\bar{A}} = A$$): $$Y = A \cdot B$$. The composite circuit functions as an AND gate.

- When $$A = 0, B = 0 \implies Y = 0 \cdot 0 = 0$$ - When $$A = 0, B = 1 \implies Y = 0 \cdot 1 = 0$$ - When $$A = 1, B = 0 \implies Y = 1 \cdot 0 = 0$$ - When $$A = 1, B = 1 \implies Y = 1 \cdot 1 = 1$$ This matches Table (1) (Option A).