Q.49 Physics ⭐ 360° Option Elimination Active

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NEET 2023 Physics Question 49 Solution

Topic: Semiconductor Electronics: Materials, Devices and Simple Circuits · Official NTA Booklet Code G5

Question

For the following logic circuit, the truth table is:

✓

Verified Against NTA Final Answer Key

Option (3) : OR Gate Truth Table (0,0→0; 0,1→1; 1,0→1; 1,1→1)

📚 Semiconductor Electronics: Materials, Devices and Simple Circuits Easy

📋 Given Parameters & Problem Setup

Inputs A, B

Input stage NOT gates giving Ā and B̄

Output stage NAND gate receiving Ā and B̄

Boolean Expression Y = (Ā · B̄)̄ = A + B

⚡

The 30-Second Exam Hall Shortcut: ⚡ De Morgan’s Inversion Hack: (Ā · B̄)̄ = A + B

⏱️ Save ~40 seconds

Bubble-NAND is an OR gate! Inputs inverted before NAND: Y = (Ā · B̄)̄ = A + B. This is an OR gate truth table (outputs 1 if ANY input is 1) in 5 seconds!

1 Trace the circuit: Input A passes through a NOT gate to become Ā.

2 Input B passes through a NOT gate to become B̄.

3 Both inverted signals feed into a NAND gate.

4 Output equation: Y = (Ā · B̄)̄.

5 Apply De Morgan’s First Theorem: (X · Z)̄ = X̄ + Z̄ ⟹ (Ā · B̄)̄ = A̿ + B̿ = A + B.

6 The entire combination is an OR gate! Its truth table outputs 0 only for (0,0), and 1 for all other inputs.

7 Select Option (3) OR Gate truth table!

🛡️

Why You Can 100% Trust This Shortcut: Digital Electronics · Boolean Algebra & De Morgan’s Laws ((Ā · B̄)̄ = A + B represents the universal NAND gate realization of an OR gate).

📐

Step-by-Step Rigorous Workflow & Mathematical Proof

Step 1

Circuit Schematic Analysis

The given digital logic circuit contains two NOT gates (inverters) connected to inputs A and B, respectively. The outputs of these two inverters, Ā and B̄, serve as the inputs to a two-input NAND gate.

\text{Inverter Outputs: } \bar{A}, \quad \bar{B}

Step 2

Formulation of Boolean Expression

A NAND gate performs an AND operation followed by a negation. Therefore, the output Y is expressed as:

Y = \overline{\bar{A} \cdot \bar{B}}

Step 3

Application of De Morgan’s Theorem

By De Morgan’s second theorem of Boolean algebra, the complement of a product of variables equals the sum of their individual complements:

\overline{X \cdot Z} = \bar{X} + \bar{Z} \implies Y = \overline{\bar{A}} + \overline{\bar{B}} = A + B

Step 4

Construction of the Resultant Truth Table

The expression Y = A + B corresponds identically to a standard OR gate:

\begin{array}{|c|c|c|c|c|c|} \hline A & B & \bar{A} & \bar{B} & \bar{A} \cdot \bar{B} & Y = \overline{\bar{A} \cdot \bar{B}} = A + B \\ \hline 0 & 0 & 1 & 1 & 1 & 0 \\ 0 & 1 & 1 & 0 & 0 & 1 \\ 1 & 0 & 0 & 1 & 0 & 1 \\ 1 & 1 & 0 & 0 & 0 & 1 \\ \hline \end{array}

⭐

360° Option Elimination Engine Key Feature

Diagnose every choice: Know exactly why the right option works and why distractors fail.

4-Option Deep Scan

1 (1)

✗ Incorrect

Verdict & Scientific Reason:

Truth table of an AND gate (Y = A · B).

⚠️

Student Fallacy (Why candidates pick this trap): Candidate forgot the inversion bubble on the NAND gate.

2 (2)

✗ Incorrect

Verdict & Scientific Reason:

Truth table of a standard NAND gate without inverted inputs.

⚠️

Student Fallacy (Why candidates pick this trap): Candidate ignored the two input inverters.

3 (3)

✓ 100% Correct

Verdict & Scientific Reason:

Accurate truth table of an OR gate: Y = A + B.

💡

Why this is airtight: None. Candidate correctly applied De Morgan’s law.

4 (4)

✗ Incorrect

Verdict & Scientific Reason:

Inverted parity table.

⚠️

Student Fallacy (Why candidates pick this trap): Candidate made logic errors during individual truth evaluations.

⚠️

NTA Trap Alert: Confusing Negative-Input NAND (OR Gate) with Negative-Input AND (NOR Gate)

Feeding inverted inputs into a NAND gate yields (Ā · B̄)̄ = A + B (an OR gate). Feeding inverted inputs into an AND gate yields Ā · B̄ = (A + B)̄ (a NOR gate). Keeping track of the bubble on the NAND gate prevents this confusion.

🛡️ How to avoid the -1 mark: Use De Morgan duality: "Bubble at inputs + Bubble at output" of an AND gate transforms it into a standard OR gate!

📖

Core NEET Syllabus Standard

National Eligibility cum Entrance Test (NEET UG) · Semiconductor Electronics: Materials, Devices and Simple Circuits Standard Benchmark

Core Scientific Principle Tested:

"By De Morgan’s laws, (Ā · B̄)̄ = A + B, which realizes the OR logic function."

Syllabus Focus: Logic Gates and Universal Gate Combinations

Preserved in Rationalized Curriculum Syllabus & Academic Standards ↗

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NEET 2023 Physics Question 49 Solution

Question

The 30-Second Exam Hall Shortcut: ⚡ De Morgan’s Inversion Hack: (Ā · B̄)̄ = A + B

Step-by-Step Rigorous Workflow & Mathematical Proof

Circuit Schematic Analysis

Formulation of Boolean Expression

Application of De Morgan’s Theorem

Construction of the Resultant Truth Table

360° Option Elimination Engine Key Feature

NTA Trap Alert: Confusing Negative-Input NAND (OR Gate) with Negative-Input AND (NOR Gate)

Core NEET Syllabus Standard

Ready to attempt under real exam pressure?

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